IBM Power8 Processor Detailed – Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed

IBM Power8 Processor Detailed – Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed

At Hot Chip 2013, IBM revealed their next generation Power8 Processor architecture featuring the most powerful and scalable performance for cloud-based data center servers. Featuring almost twice the level of performance as 2012′s Power 7 chip, the Power8 Processor would take high-performance computing for enterprise markets to the next level.

IBM Power8 Processor HPC Architecture Detailed

The technical details presented at the Hot Chip 2013 conference by IBM showcased the Power8 Processor featuring 12 cores with the new 8-Way simultaneous multithreading (SMT) compared to the 4-Way SMT in Power7 processors. Being the most high-performance chip that IBM has to offer, the components are scattered across a 22nm die featuring silicon-on-insulator technology spread across an area of 650mm²  which is quite huge.

The Power8 Processor also features a 16 Execution Pipeline followed with 64K data cache per-core and 32K instruction cache. On the cache front, the new processor has 512 KB SRAM L2 cache per core, 96 MB eDRAM shared L3 cache and also 128 MB of eDRAM L4 cache that’s situated off-die unlike the on-board eDRAM on Haswell processors featuring GT3e iGPUs.

“The entire Power-based ecosystem has lost many supporters in the industry like Freescale, AppliedMicro, Xbox and Playstation, so Power 8 is very important to get right,” said Patrick Moorhead, an analyst at Moor Insights & Strategy. “It will be a real challenge to fight both Intel and AMD in this space given their scale, and very important to IBM given they are banking on Power architecture for the their platform future.  We believe IBM will exit the X86 server market and sell their line to Lenovo, making Power 8 critical to IBM’s future success.” IBM

Memory support is offered in transnational memory and support for Crypto & memory expansion. The chip offers a total bandwidth of 230 GB/s. An On-Chip power management micro-controller is used for regulating power and voltage delivery to the chip while each core has its share on integrated voltage regulator modules (VRM) which is yet another similar approach as Intel’s Haswell processors.



Along with its tremendous design, Power8 processor would also use a Coherently Allocated Processor Interface or CAPI for short featuring coherent memory addressing for CPUs and external co-processors such as NVIDIA’s Tesla or the Intel Knight’s Landing and Ferry. There’s no mention of TDP at the moment but IBM has been offering their previous Power series processors with TDPs of around 200W, with the new 22nm architecture in play the TDP should drop down a bit while improving the performance tremendously over Power7.

This article originally appeared on WCCFTech (Link)